1. Field of the Invention
The present invention relates to a synchronous clock generation apparatus and synchronous clock generation method for generating a clock synchronized with an input signal. More specifically, the present invention relates to the synchronous clock generation apparatus and synchronous clock generation method for generating a clock synchronized with a horizontal synchronizing signal of a video signal.
2. Description of the Related Art
As a synchronous clock generation apparatus and synchronous clock generation method for generating a clock synchronized with an input signal, a horizontal synchronous clock generation apparatus for generating a clock synchronized with a horizontal synchronizing signal which is added to a video signal is disclosed in, for example, the Japanese Published Patent Application No. 2001-94821.
FIG. 12 is a block diagram illustrating a configuration of a sampling clock generation circuit suggested in the above-described Patent Document. In FIG. 12, an analog video signal S1201 to which a horizontal synchronizing signal is added is input to a video signal input terminal 1201. An A/D converter 1202 subjects the input analog video signal S1201 to digital conversion using a horizontal synchronous clock S1216 outputted from a multiplication circuit 1216 described later as a reference of sampling, and outputs a digital video signal S1202. A horizontal synchronization separator circuit 1203 separates a horizontal synchronizing signal from the digital video signal S1202 and outputs the separated horizontal synchronizing signal S1203. A pulse generation circuit 1204 counts the horizontal synchronous clocks S1216 outputted from the multiplication circuit 1216, described later, up to the number determined for each broadcast system for the input analog video signal S1201 to generate a horizontal synchronizing pulse signal S1204 and outputs the same. A multiplier 1205 multiplies the input horizontal synchronizing signal S1203 by the horizontal synchronizing pulse signal S1204 and outputs the result as multiplication data S1205. A digital LPF (low-pass filter) 1206 outputs, as correction data S1206, data which is obtained by eliminating high frequency components from the input multiplication data S1205 and extracting only DC (direct current) components.
The adder 1209 adds the correction data S1206 and a digital control signal S1218 which is supplied from a digital input terminal 1218 to output addition data S1209. Here, the digital control signal S1218 is data for determining a frequency of the horizontal synchronous clock outputted from the multiplication circuit 1216, described later, in a case where the correction data S1206 is not outputted from the digital LPF 1206, that is, a free-run frequency. An address generation circuit 1210 sequentially performs accumulation arithmetic of the input addition data S1209 to calculate an accumulated value. Here, the accumulated value is a value for which a carry-out signal is not used. Further, the address generation circuit 1210 outputs, as address data S1210, data which is obtained by dividing the accumulated value such that the accumulated value is adapted to an address of a SIN wave data table in the ROM (Read Only Memory) circuit 1211 described later. The frequency of the address data S1210 becomes faster as the addition data S1209 becomes larger, while the frequency of the address data S1210 becomes slower as the addition data S1209 becomes smaller. The ROM circuit 1211 holds a SIN wave data table, and when the address data S1210 is input, the ROM circuit 1211 refers to the SIN wave data which are held therein for each address and outputs a digital SIN wave signal S1211. A D/A converter 1212 converts the input digital SIN wave signal S1211 into an analog signal to output the converted signal as an analog SIN wave signal S1212. A multiplication circuit 1216 outputs, as a horizontal synchronous clock S1216, a clock signal which is obtained by performing an integral multiplication of a frequency of the input analog SIN wave signal S1212. The adder 1209, address generation circuit 1210, ROM circuit 1211, D/A converter 1212, and multiplication circuit 1216 constitute a VCO (voltage-controlled oscillator). The horizontal synchronous clock S1216 is supplied to each of the various external video signal processing units and supplied to the A/D converter 1202 and the pulse generation circuit 1204, as described above.
FIG. 13 is a diagram illustrating a clock frequency characteristic curve for explaining a performance of the sampling clock generation circuit disclosed in the above-described patent Document. In FIG. 13, the axis of abscissa indicates a desired clock frequency or a clock frequency which is primarily obtained when a clock frequency is completely synchronized with a horizontal synchronizing signal of a video signal, while the axis of ordinate indicates a generated clock frequency which is actually outputted from the multiplication circuit 1216 in the sampling clock generation circuit. The clock frequency characteristic curve S1321 indicates a relationship between the desired clock frequency and the generated clock frequency. The clock frequency characteristic curve S1321 is of step shape, and the desired clock frequencies consecutively change while the generated clock frequencies take non-consecutive values. The frequency lock range S1322 indicates a range of the generated clock frequencies which can be frequency-locked. The frequency lock precision S1323 is a precision of the generated clock frequency obtained with respect to the desired clock frequency, and here it is represented as a difference in frequency between the adjacent generated clock frequencies. When the frequency lock precision S1323 is high, that is, the difference in frequency between the adjacent generated clock frequencies is small, the generated clock frequency can be frequency-locked to the generated clock frequency close to the desired clock frequency with higher precision. The frequency S1324 is a generated clock frequency in the case of no correction data S1206 being supplied from the digital LPF 1206.
As shown in FIG. 13, when the desired clock frequency is F1301, the generated clock frequency is F1302. Further, when the desired clock frequency is F1303, the generated clock frequency is F1304. Further, when the desired clock frequency is F1307, the generated clock frequency is F1308. Moreover, when the desired clock frequency is F1305, the generated clock frequency is F1306.
Here, the frequency lock range S1322 depends on the gain of the digital LPF 1206. That is, when the gain of the digital LPF 1206 is larger, the variation in frequency of the address generation circuit 1210 becomes wider, and thereby the variation in generated clock frequency becomes wider and the frequency lock range S1322 becomes wider.
Further, the frequency lock precision S1323 depends on the number of bits of the correction data S1206 which is an output from the digital LPF 1206 and a gain of the digital LPF 1206. That is, as the number of bits of the correction data S1206, which is an output from the digital LPF 1206, is larger, the number of steps which the generated clock frequencies can take within the frequency lock range S1322 is larger, and thereby the frequency lock precision is made higher. On the other hand, when the number of bits of the correction data S1206 which is an output from the digital LPF 1206 is constant and the number of steps which the generated clock frequencies can take within the frequency lock range S1322 is constant, as the gain of the digital LPF 1206 becomes larger, the frequency lock range becomes wider, and thereby the frequency lock precision is made lower.
However, in the prior art sampling clock generation circuit, as disclosed in the above Patent Document, for example, as shown in FIG. 13, when the desired clock frequency is between F1303 and F1307, the obtained generated clock frequency is either F1304 or F1308 which are frequencies different from each other by the frequency lock precision, and the generated clock frequency cannot take the intermediate value. That is, the generated clock frequency cannot be obtained with precision higher than the frequency lock precision. The frequency lock precision is set on the basis of the number of output bits and gain of the digital LPF 1206, and these values are determined depending on the circuit configuration of the digital LPF 1206, and cannot be easily changed during the operation. Accordingly, there is a problem that the sampling clock generation circuit disclosed in the above-described Patent Document can generate only the generated clock frequency which is dependent upon the frequency lock precision which is determined by the circuit configuration.
In addition, as shown in FIG. 13, when the desired clock frequency is a frequency F1305 which is higher than the generated clock frequency F1306, which is an upper limit of the frequency lock range, the generated clock frequency which is obtained by the horizontal synchronous clock generation apparatus is locked to F1306. That is, the generated clock frequency cannot be a frequency outside the frequency lock range, and therefore when the desired clock frequency is a frequency higher than the generated clock frequency, which is an upper limit of the frequency lock range, the generated clock frequency is locked to a generated clock frequency, which is an upper limit of the frequency lock range. The frequency lock range is set depending on the gain of the digital LPF 1206, and the value of the gain is determined depending on the circuit configuration of the digital LPF 1206, and cannot be easily changed during the operation. Accordingly, there is a problem that in the sampling clock generation circuit disclosed in the above-described Patent Document, when the desired clock frequency is a frequency outside the frequency lock range, the generated clock frequency cannot trace the desired clock frequency, thereby generating only the generated clock frequencies which are dependent upon the frequency lock range.
Then, it can be assumed that the above-described problem is solved by expanding bits of data outputted from the digital LPF 1206. However, in this case, there is a drawback that the circuit scale is substantially increased.